The present invention relates generally to nonvolatile memories and particularly to electrically erasable nonvolatile memories.
Semiconductor memory devices may be characterized to be volatile or nonvolatile, depending on whether a memory device is able to retain the contents of the memory on removal of power to the device. Typical well-known examples of volatile memory devices include random access memories RAM's such as SRAM's and DRAM's, and examples of nonvolatile memory (NVM) devices include read only memories (ROM's). There are many types of ROM devices including erasable programmable read only memories (EPROMs), electrically erasable and programmable read only memories (EEPROMs) and flash EEPROM memories. Typically EPROMs are erasable through light exposure and are electrically programmable. Conventional EEPROMs have the same programming functionality, however instead of being light erasable they may be erased and programmed by an electron tunneling process facilitated by an on-chip electrical signal. Thus, information may be stored in these NVM devices, retained when the power is off, and the devices may be erased for reprogramming, as necessary, using appropriate techniques. A memory cell in a flash memory device may be individually programmed. Several memory cells may be advantageously erased as a block, typically resulting in improved performance compared to conventional EEPROMs.
Presently, flash memories have gained considerable popularity due to their smaller size, lower power consumption and improved read/write performance. For example, flash memories are often utilized to provide on-chip memory for portable devices such as cellular phones, digital cameras, audio/video recorders, modems, SMART cards and the like where it is desirable to store information that may need fast updating.
The typical data storage element of an EEPROM memory cell is a floating gate transistor, which is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source and drain regions of the cell. Data is represented by a charge stored on the floating gate and the resulting conductivity obtained between source and drain regions. A floating gate memory cell may be formed in a P-type substrate with an N-type diffused source region and an N-type drain diffusion formed in the region. A floating gate, typically made of doped polysilicon, is located over the channel region and is electrically isolated from the other cell elements by oxide. For example, a thin gate oxide may be located between the floating gate and the channel region. A control gate is typically located over the floating gate and may also be made of doped polysilicon. The control gate is typically separated from the floating gate by a dielectric layer.
Basic operations of the EEPROM memory cell may be described as: a) programming, b) erasing, and c) reading. Programming usually refers to transferring a charge to the floating gate. Erasing usually refers to removing the charge from the floating gate and reading involves sensing an electrical signal of the cell to determine if the device is in a programmed or an erased state.
Functionality and fabrication method of a flash memory device such as a conventional N-channel, stack-gate memory cell is well known. However, some of these traditional techniques often result in well-known problems such as creating over-erase and hot-hole trap conditions often resulting in low programming speed and low injection efficiency. This leads to the degradation of the endurance performance of the memory cell.
Thus, a need exists to provide an improved memory cell that offers: a) protection from over-erase and hot-hole trap conditions, and b) an improved programming speed and higher injection efficiency. Additionally, it would be desirable for the improved memory cell to offer a higher endurance performance when compared to the traditional memory cell.